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5 v, 12-bit nanodac, serial interface in msop and lfcsp packages AD5626 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?20072009 analog devices, inc. all rights reserved. features 8-lead msop and 8-lead lfcsp packages complete voltage output with internal reference 1 mv/bit with 4.095 v full scale 5 v single-supply operation no external components required 3-wire serial interface, 20 mhz data loading rate low power: 2.5 mw applications portable instrumentation digitally controlled calibration servo controls process control equipment pc peripherals general description the AD5626, a member of the nano dac? family, is a complete serial input, 12-bit, voltage output digital-to-analog converter (dac) designed to operate from a single 5 v supply. it contains the dac, input shift register and latches, reference, and a rail- to-rail output amplifier. the AD5626 monolithic dac offers the user low cost and ease of use in 5 v only systems. coding for the AD5626 is natural binary with the msb loaded first. the output op amp can swing to either rail and is set to a range of 0 v to 4.095 v for a one-millivolt-per-bit resolution. it is capable of sinking and sourcing 5 ma. an on-chip reference is laser trimmed to provide an accurate full-scale output voltage of 4.095 v. this part features a serial interface that is high speed, three- wire, dsp compatible with data in (sdin), clock (sclk), and load strobe ( ldac ). there is also a chip-select pin for connecting multiple dacs. the clr input sets the output to zero scale at power on or upon user demand. the AD5626 is specified over the extended industrial tempera- ture range (C40c to +85c). the AD5626 is available in msop and lfcsp surface-mount packages. functional block diagram 06757-001 ref dac register AD5626 input register 12-bit dac output buffer ldac v ou t clr cs sclk sdin gnd v dd figure 1.
AD5626 rev. a | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristics ............................................................. 3 timing characteristics ................................................................ 4 absolute maximum ratings ............................................................ 5 esd caution .................................................................................. 5 pin configurations and function descriptions ........................... 6 typical performance characteristics ............................................. 7 theory of operation ...................................................................... 10 dac section ................................................................................ 10 amplifier section........................................................................ 10 output section ............................................................................ 10 power supply ............................................................................... 10 timing and control ................................................................... 11 applications information .............................................................. 12 power supplies, bypassing, and grounding ........................... 12 unipolar output operation ...................................................... 12 operating the AD5626 on 12 v or 15 v supplies only ........ 13 measuring offset error ............................................................. 13 bipolar output operation ......................................................... 13 generating a negative supply voltage .................................... 15 a single-supply, programmable current source .................. 15 galvanically-isolated interface ................................................. 15 microprocessor interfacing ....................................................... 16 outline dimensions ....................................................................... 17 ordering guide .......................................................................... 17 revision history 1/09rev. 0 to rev. a change to full-scale tempco paramter and full-scale voltage (min) parameter ................................................................. 3 12/07revision 0: initial version
AD5626 rev. a | page 3 of 20 specifications electrical characteristics @ v dd = 5.0 v 5%, ?40c t a +85c, b grade device, unless otherwise noted. table 1. parameter symbol condition min typ max unit static performance resolution n 12 bits relative accuracy inl ?1 1/4 +1 lsb differential nonlinearity dnl no missing codes ?1 3/4 +1 lsb zero-scale error v zse data = 0x000 1/2 3 lsb full-scale voltage v fs data = 0xfff 1 4.079 4.095 4.111 v full-scale tempco 2 , 3 tcv fs 20 ppm/c analog output output current i out data = 0x800 5 7 ma load regulation at midscale l reg r l = 402 to , data = 0x800 1 3 lsb capacitive load c l no oscillation 2 500 pf logic inputs logic input low voltage v il 0.8 v high voltage v ih 2.4 v input leakage current i il 10 a input capacitance c il 10 pf ac characteristics 2 voltage output settling time t s to 1 lsb of final value 3 16 s dac glitch 15 nv-s digital feedthrough 15 nv-s supply characteristics positive supply current i dd v ih = 2.4 v, v il = 0.8 v, no load 1.5 2.5 ma v dd = 5 v, v il = 0 v, no load 0.5 1 ma power dissipation p diss v ih = 2.4 v, v il = 0.8 v, no load 7.5 12.5 mw v dd = 5 v, v il = 0 v, no load 2.5 5 mw power supply sensitivity pss v dd = 5% 0.002 0.004 %/% 1 includes internal vo ltage reference error. 2 these parameters are guaranteed by design and not subject to production testing. 3 the settling time specification does not apply for negative going transitions within the last 6 lsbs of ground. some devices e xhibit double the typical settling time in this 6 lsb region.
AD5626 rev. a | page 4 of 20 timing characteristics @ v dd = 5.0 v 5%, ?40c t a +85c, unless otherwise noted. table 2. parameter 1 , 2 limit at t min , t max unit description t ch 30 ns min clock width high t cl 30 ns min clock width low t ldw 20 ns min load pulse width t ds 15 ns min data setup t dh 15 ns min data hold t clrw 30 ns min clear pulse width t ld1 15 ns min load setup t ld2 10 ns min load hold t css 30 ns min select t csh 20 ns min deselect 1 these parameters are guaranteed by design and not subject to production testing. 2 all input control signals are specified with tr = tf = 5 ns (10% to 90% of 5 v) and timed from a voltage level of 1.6 v. timing diagram 06757-002 sdin d11 d10 d9 d8 d7 d6 d5 d4 1 lsb error band d3 d2 d1 do t csh t ld2 sclk cs ldac t ld1 t cl t ds t ch t dh t s t s t clrw t ldw t css sdin sclk ldac clr fs v out zs figure 2. timing diagram
AD5626 rev. a | page 5 of 20 absolute maximum ratings table 3. parameter rating v dd to gnd ?0.3 v to +10 v logic inputs to gnd ?0.3 v to v dd + 0.3 v v out to gnd ?0.3 v to v dd + 0.3 v i out short circuit to gnd 50 ma package power dissipation (t j max ? t a )/ ja thermal resistance ( ja ) 8-lead msop 220c/w 8-lead lfcsp 62c/w maximum junction temperature (t j max) 150c operating temperature range ?40c to +85c storage temperature range ?65c to +150c lead temperature jedec industry standard soldering j-std-020 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
AD5626 rev. a | page 6 of 20 pin configurations and function descriptions 0 6757-003 v dd 1 cs 2 sclk 3 sdin 4 v out 8 gnd 7 clr 6 ldac 5 AD5626 top view (not to scale) 0 6757-004 v dd 1 sclk 3 sdin 4 v out 8 gnd 7 AD5626 top view (not to scale) cs 2 clr 6 ldac 5 figure 3. 8-lead msop pin configuration figure 4. 8-lead lfcsp pin configuration table 4. pin function descriptions pin no. mnemonic description 1 v dd positive supply. nominal value 5 v 5%. 2 cs chip select. active low input. 3 sclk clock input. clock input for th e internal serial input shift register. 4 sdin serial data input. data on this pin is clocked into the internal serial register on positive clock edges of the sclk pin. the most significant bit (msb) is loaded first. 5 ldac serial register data write to dac register. active low input that writes the serial register data into the dac register. asynchronous input. 6 clr clear dac register. active low digital input that clears the dac register to zero, setting the dac to minimum scale. asynchronous input. 7 gnd ground. analog ground for the dac. this also serves as the digital logic ground reference voltage. 8 v out voltage output from the dac. fixed output voltage range of 0 v to 4.095 v with 1 mv/lsb. an internal temperature stabilized reference maintains a fixed full-scale voltage independent of time, temperature, and power supply variations. table 5. control logic truth table 1 cs 2 , 3 clk 2 clr ld 4 serial shift register function dac register function h x h h no effect latched l l h h no effect latched l h h h no effect latched l + h h shift-register-data advanced one bit latched + l h h shift-register-data advanced one bit latched h x h C no effect updated with current shift register contents h x h l no effect transparent h x l x no effect loaded with all zeros h x + h no effect latched all zeros 1 + indicates a positive logic transition; C indicates a negative logic transition; x = dont care. 2 cs and clk are interchangeable. 3 returning cs high avoids an additional false clock of serial data input. 4 do not clock in serial data while ld is low.
AD5626 rev. a | page 7 of 20 typical performance characteristics 5 0 10 100k 06757-005 load resistance ( ? ) output voltage (v) 100 1k 10k 4 3 2 1 v dd = 5v t a = 25c r l tied to agnd data = 0xfff r l tied to 5v data = 0x000 figure 5. output voltage vs. load 100 0.0001 11 06757-006 output sink current (a) output pull-down voltage (mv) 0 0 0 10 100 10 0.1 1 0.01 0.001 +85c +25c ?40c figure 6. output pull-down voltage vs. output sink current capability 80 ?60 06757-007 output voltage (v) output current (ma) 60 40 20 0 ?20 ?40 1.0 02 . 04 . 0 3.0 1.5 0.5 2.5 4.5 3.5 5.0 figure 7. short-circuit current 06757-008 ch1 5.00v ch2 100mv m2.00ms a ch1 210v 1 figure 8. broadband noise 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 05 06757-009 logic voltage value (v) supply current (ma) . 0 1.0 2.0 3.0 4.0 0.5 1.5 2.5 3.5 4.5 figure 9. supply current vs. logic input voltage 80 ?10 0 10 100k 06757-010 frequency (hz) power supply rejection (db) 100 1k 10k 70 30 50 60 20 40 10 figure 10. power supply rejection vs. frequency
AD5626 rev. a | page 8 of 20 5.0 4.0 0.01 10 06757-011 output load current (ma) v dd min (v) 0.1 1 4.8 4.6 4.4 4.2 v fs 1 lsb data = 0xfff t a = 25c proper operation when v dd supply voltage is above curve figure 11. minimum supply voltage vs. load 06757-012 time (ns) v out (v) 2.07 2.06 2.05 2.04 2.11 2.10 2.09 2.08 2.03 4.0 0 0.5 1.0 1.5 2.0 2.5 3.5 3.0 0x7ff 0x800 0x800 0x7ff figure 12. midscale dac glitch performance 06757-013 output ch2 source 2.90v offset 1.00v/div verticle scale 105.758s position 50.0s/div horizontal scale 2 figure 13. large signal settling time 06757-014 output ch1 ch2 source ?1.95v 3.9875mv offset 2.00v/div 200mv/div verticle scale 22.725s 22.725s position 5.0s/div 5.0s/div horizontal scale 1 2 ldac figure 14. rise time detail ch1 ch2 source ?1.95v 87.6mv offset 2.00v/div 200mv/div verticle scale 22.725s 22.725s position 5.0s/div 5.0s/div horizontal scale 06757-015 output 1 2 ldac figure 15. fall time detail 0.20 ?0.15 0 4000 06757-016 code inl (lsb) 0.15 0.10 0.05 0 ?0.05 ?0.10 500 1000 1500 2000 2500 3000 3500 v dd = 5v +25c ?40c +85c figure 16. integral linearity error vs. digital code
AD5626 rev. a | page 9 of 20 10 0.01 10 100k 06757-020 frequency (hz) output noise density (v/ hz) 100 1k 10k 0.1 1 v dd = 5v no load data = 0xfff 60 0 ?12 06757-017 total unadjusted error (mv) nnumber of units 50 40 30 20 10 ?8 ?4 0 4 8 12 tue = inl + zs + fs ss = 300 units t a = 25c figure 17. total unadjusted error histogram figure 20. output voltage noise vs. frequency 4.115 4.075 ?50 125 06757-018 temperature (c) full-scale output (v) 4.110 4.105 4.100 4.095 4.090 4.085 4.080 ?25 0 25 50 75 100 v dd = 5v no load ss = 300 units avg + 3 avg avg ? 3 5 ?5 01 06757-021 hours of operation at 125c output voltage change (mv) 2 0 0 4 3 2 1 0 ?1 ?2 ?3 ?4 200 400 600 800 1000 135 units tested average range readings normalized to zero hour time point figure 18. full-scale output voltage vs. temperature figure 21. long-term drif t accelerated by burn-in 0.50 0.35 0.40 0.45 0.30 0.25 0.20 0.15 0.10 0.05 0 ?40 06757-019 temperature (c) zero scale (mv) ?20 0 20 40 60 80 1.6 0 ?40 06757-022 temperature (c) supply current (ma) ?200 20406080 1.4 1.2 1.0 0.8 0.6 0.4 0.2 v dd = 4.75v v dd = 5v v dd = 5.25v figure 19. zero-scale voltage vs. temperature figure 22. supply current vs. temperature
AD5626 rev. a | page 10 of 20 theory of operation the AD5626 is a complete, ready-to-use, 12-bit digital-to-analog converter (dac). it contains a voltage-switched, 12-bit, laser- trimmed dac, a curvature-corrected band gap reference, a rail-to-rail output op amp, a dac register, and a serial data input register. the serial data interface consists of an sclk, serial data in (sdin), and a load strobe ( ldac ). this basic 3-wire interface offers maximum flexibility for interface to the widest variety of serial data input loading requirements. in addition, a cs select is provided for multiple packaging loading and a power-on-reset clr pin to simplify start or periodic resets. dac section the dac is a 12-bit voltage mode device with an output that swings from the gnd potential to the 2.5 v internal band gap voltage. it uses a laser trimmed, rail-to-rail ladder which is switched by n-channel mosfets. the output voltage of the dac has a constant resistance independent of digital input code. the dac output internally connects to the rail-to-rail output op amp. amplifier section a low power consumption, precision amplifier buffers the dac output. this amplifier contains a differential pnp pair input stage that provides low offset voltage and low noise, as well as the ability to amplify the zero-scale dac output voltages. the rail-to-rail amplifier is configured with a gain of 1.6384 (= 4.095 v/2.5 v) to set the 4.095 v full-scale output (1 mv/lsb). see figure 23 for an equivalent circuit schematic of the analog section. 06757-023 2r 2r 2r r2 r 2r 2r r r1 v out buffer band gap reference 2.5v spdt n-channel fet switches rail-to-rail output amplifier a v = 1.638 (= 4.095v/2.5v) v oltage switched 12-bit rail-to-rail converter figure 23. equivalent AD5626 schematic of analog section the op amp has a 16 s typical settling time to 0.01%. there are slight differences in settling time for negative slewing signals vs. positive slewing signals. see the oscilloscope photos in the typical performance characteristics section of this data sheet. output section the rail-to-rail output stage of this amplifier is designed to provide precision performance when operating near either power supply. 06757-024 p-ch v dd v out agnd n-ch figure 24. equivalent analog output circuit figure 24 shows an equivalent output schematic of the rail-to- rail amplifier with its n-channel pull-down fets that pull an output load directly to gnd. the output sourcing current is provided by a p-channel pull-up device that can supply gnd terminated loads, especially at the low supply tolerance values of 4.75 v. figure 5 and figure 6 provide information on output swing performance near ground and full-scale as a function of load. in addition to resistive load driving capability, the amplifier has also been carefully designed and characterized for up to 500 pf capacitive load driving capability. power supply the very low power consumption of the AD5626 is a direct result of a circuit design optimizing use of the cbcmos process. by using the low power characteristics of the cmos for the logic, and the low noise, tight matching of the complementary bipolar transistors, good analog accuracy is achieved. for power consumption sensitive applications, it is important to note that the internal power consumption of the AD5626 is strongly dependent on the actual logic input voltage levels present on the sdin, cs , ldac , and clr pins. because these inputs are standard cmos logic structures, they contribute static power dissipation dependent on the actual driving logic v oh and logic v ol voltage levels. the graph in shows the effect on total AD5626 supply current as a function of the actual value of input logic voltage. consequently, use of cmos logic vs. ttl minimizes power dissipation in the static state. a v il = 0 v on the sdin, figure 9 cs , and clr pins provides the lowest standby power dissipation of 2.5 mw (500 a 5 v). as with any analog system, it is recommended that the AD5626 power supply be bypassed on the same pc card that contains the chip. figure 10 shows the power supply rejection vs. frequency performance. this should be taken into account when using higher frequency, switched mode power supplies with ripple frequencies of 100 khz and higher. one advantage of the rail-to-rail output amplifier used in the AD5626 is the wide range of usable supply voltage. the part is fully specified and tested over temperature for operation from 4.75 v to 5.25 v. if reduced linearity and source current capa- bility near full scale can be tolerated, operation of the AD5626 is possible down to 4.3 v. the minimum operating supply
AD5626 rev. a | page 11 of 20 voltage vs. load current plot, shown in figure 11 , provides information for operation below v dd = 4.75 v. timing and control the AD5626 has a separate serial input register from the 12-bit dac register that allows preloading of a new data value into the serial register without disturbing the present dac output voltage. after the new value is fully loaded in the serial input register, it can be asynchronously transferred to the dac register by strobing the ldac pin. the dac register uses a level sensitive ldac strobe that should be returned high before any new data is loaded into the serial input register. at any time, the contents of the dac register can be reset to zero by strobing the clr pin that causes the dac output voltage to go to zero volts. details all of the timing requirements together with , the control logic truth table. figure 2 table 5
AD5626 rev. a | page 12 of 20 applications information power supplies, bypassing, and grounding all precision converter products require careful application of good grounding practices to maintain full rated performance. because the AD5626 has been designed for 5 v applications, it is ideal for those applications under microprocessor or micro- computer control. in these applications, digital noise is prevalent; therefore, special care must be taken to ensure that its inherent precision is maintained by exercising particularly good engineering judgment when addressing the power supply, grounding, and bypassing issues using the AD5626. use a well-filtered and regulated power supply for the AD5626. the device has been completely characterized for a 5 v supply with a tolerance of 5%. because a 5 v logic supply is almost universally available, it is not recommended to connect the dac directly to an unfiltered logic supply without careful filtering. tapping a logic circuit supply for the dac supply is unwise because fast logic with nanosecond transition edges induce high current pulses. the high transient current pulses can generate glitches hundreds of millivolts in amplitude due to wiring resistances and inductances. this high frequency noise corrupts the analog circuits internal to the dac and causes errors. even though their spike noise is lower in amplitude, directly tapping the output of a 5 v system supply can cause errors because these supplies are of the switching regulator type that can and do generate a great deal of high frequency noise. there- fore, power the dac and any associated analog circuitry directly from the system power supply outputs using appropriate filtering. figure 25 illustrates how a clean, analog-grade supply can be generated from a 5 v logic supply using a differential lc filter with separate power supply and return lines. with the values shown, this filter can easily handle 100 ma of load current without saturating the ferrite cores. higher current capacity can be achieved with larger ferrite cores. for lowest noise, all electrolytic capacitors should be of the low equivalent series resistance (esr) type. 06757-025 ferrite beads: 2 turns +5v +5v return ttl/cmos logic circuits 5v power supply 100f elect. 10-20f tant. 0.1f cer. + + figure 25. properly filtering a 5 v logic supply yields a high quality analog supply to fit the AD5626 in an 8-lead package, only one ground connection to the device is accommodated. the ground connection of the dac serves as the return path for supply currents as well as the reference point for the digital input thresholds. the ground connection also serves as the supply rail for the internal voltage reference and the output amplifier. therefore, to minimize errors, connect the ground connection of the AD5626 to a high quality analog ground, such as the one previously described. generous bypassing of the dacs supply effectively reduces supply line induced errors. local supply bypassing consisting of a 10 f tantalum electrolytic capacitor in parallel with a 0.1 f ceramic capacitor is recommended. connect the decoupling capacitors between the dac supply pin (pin 1) and the analog ground (pin 7). figure 26 shows how the ground and bypass connections should be made to the AD5626. 06757-026 cs clr sclk ldac sdin 2 8 6 5 3 4 v out v out 1 7 v dd 5 v gnd AD5626 + 10f 0.1f to analog ground figure 26. recommended grounding an d bypassing scheme for the AD5626 unipolar output operation this is the basic mode of operation for the AD5626. as shown in figure 27 , the AD5626 is designed to drive loads as low as 2 k in parallel with 500 pf. the code table for this operation is provided in table 6 . 06757-027 cs clr sclk ldac sdin 2 8 6 5 3 4 v out 1 7 v dd gnd AD5626 10f 2k? 500pf 0.1f 5 v + 0v v out 4.095v figure 27. unipolar output operation table 6. unipolar code table hexadecimal number in dac register decimal number in dac register analog output voltage (v) fff 4095 4.095 801 2049 2.049 800 2048 2.048 7ff 2047 2.047 000 0 0
AD5626 rev. a | page 13 of 20 operating the AD5626 on 12 v or 15 v supplies only although the AD5626 has been specified to operate on a single, 5 v supply, a single 5 v supply may not be available in many applications. because the AD5626 consumes no more than 2.5 ma maximum, an integrated voltage reference, such as the adr02, can be used as the 5 v supply for the AD5626. see figure 28 for the circuit configuration. notice that the output voltage of the reference requires no trimming because of the excellent load regulation and tight initial output voltage tolerance of the adr02. although the maximum supply current of the AD5626 is 2.5 ma, local bypassing of the adr02 output with at least 0.1 f at the dac voltage supply pin is recommended to prevent the internal digital circuits of the dac from affecting the internal voltage reference of the dac. 06757-028 cs clr sclk ldac sdin 2 8 6 5 3 4 1 7 v dd gnd AD5626 0.1f v out 12v or 15 v 1f adr02 2 4 6 figure 28. operating the AD5626 on 12 v or 15 v supplies using an adr02 voltage reference measuring offset error one of the most commonly specified endpoint errors associated with real world nonideal dacs is offset error. in most dac testing, the offset error is measured by applying the zero-scale code and measuring the output deviation from 0 v. there are some dacs where offset errors are present but not observable at the zero scale because of other circuit limitations (for example, zero coinciding with single-supply ground). in these dacs, nonzero output at zero code cannot be read as the offset error. in the AD5626, for example, the zero-scale error is specified to be 3 lsbs. because zero scale coincides with zero volt, it is not possible to measure negative offset error. 0 6757-029 cs clr sclk v? lda c sdin 2 8 6 5 3 4 v out 1 7 v dd gnd AD5626 0.1f 5 v 200a, max r v out set code = 0x000 and measure v out figure 29. measuring zero-scale or offset error by adding a pull-down resistor from the output of the AD5626 to a negative supply as shown in figure 29 , offset errors can be read at zero code. this configuration forces the output p-channel mosfet to source current to the negative supply thereby allowing the designer to determine in which direction the offset error appears. the value of the resistor should be such that, at zero code, current through the resistor is 200 a, maximum. bipolar output operation although the AD5626 has been designed for single-supply operation, bipolar operation is achievable using the circuit illustrated in figure 30 . the circuit uses a single-supply, rail- to-rail op295 op amp and the ref03 to generate the ?2.5 v reference required to level shift the dac output voltage. note that the ?2.5 v reference is generated without the use of precision resistors. the circuit configuration provides an output voltage in the range of ?5 v v out +5 v and is coded in comple- mentary offset binary. although each dac lsb corresponds to 1 mv, each output lsb has been scaled to 2.44 mv. table 7 lists the relationship between the digital codes and output voltage. the transfer function of the circuit is given by r2 r4 r1 r4 codedigital v o + ?= 5.2 mv1 and, for the circuit values shown, becomes v o = ?2.44 mv digital code + 5 v
AD5626 rev. a | page 14 of 20 cs clr sclk ldac sdin 2 8 6 5 3 4 v out 1 7 v dd gnd AD5626 0.1f 10f +5 v +5v + a2 8 4 5 7 6 r1 10k ? r2 12.7k ? p1 10k ? r3 247k ? 2.5v trim zero-scale adjust ?2.5v ?5v ?5v v o +5 v + ? r4 23.7k ? full-scale adjust p3 500? p2 10k ? a1 3 1 2 100? a1, a2 = 1/2 op295 ?2.5v + ? +5v 0.1f adr03 2 4 6 5 0.01f 06757-030 figure 30. bipolar output operation 06757-031 cs clr sclk ldac sdin 2 8 6 5 3 4 v out 1 7 v dd gnd AD5626 +5v 0.1f +5v +2.5v a1 8 4 3 1 2 r3 r4 ?5v v o + ? r2 +5 v 0.1f adr03 2 4 6 r1 2.5v 5v 15k ? + 274 ? r1 10k ? 10k ? 43.2k ? + 499 ? 10k ? 20k ? r2 1 0 k ? 1 0 k ? r 3 r4 v out range a1 = 1/2 op295 figure 31. bipolar output operation without trim table 7. bipolar code hexadecimal number in dac register decimal number in dac register analog output voltage (v) fff 4095 ?4.9976 801 2049 ?2.44e ? 3 800 2048 0 7ff 2047 +2.44e ? 3 000 0 +5 to maintain monotonicity and accuracy, r1, r2, and r4 should be selected to match within 0.01% and must all be of the same (preferably metal foil) type to assure temperature coefficient matching. mismatching between r1 and r2 causes offset and gain errors whereas an r4 to r1 or r4 to r2 mismatch yields gain errors. for applications that do not require high accuracy, the circuit illustrated in figure 31 can also be used to generate a bipolar output voltage. in this circuit, only one op amp is used and no potentiometers are used for offset and gain trim. the output voltage is coded in offset binary and is given by r1 r2 r1 r2 r4r3 r4 codedigital v o 5.21 mv1
AD5626 rev. a | page 15 of 20 for the 2.5 v output range and the circuit values shown in the table in figure 31 , the transfer equation becomes v o = 1.22 mv digital code ? 2.5 v similarly, for the 5 v output range, the transfer equation becomes v o = 2.44 mv digital code ? 5 v generating a negative supply voltage some applications may require bipolar output configuration but only have a single power supply rail available. this is very common in data acquisition systems using microprocessor- based systems. in these systems, only 12 v, 15 v, and/or 5 v are available. figure 32 shows a method for generating a negative supply voltage using one cd4049, a cmos hexadecimal inverter, and operating on 12 v or 15 v. the circuit is essentially a charge pump where two of the six inverters are used as an oscillator. for the values shown, the frequency of oscillation is approx- imately 3.5 khz and is fairly insensitive to supply voltage because r1 > 2 r2. the remaining four inverters are wired in parallel for higher output current. the square wave output is level translated by c2 to a negative-going signal rectified using a pair of 1n4001s, and then filtered by c3. with the values shown, the charge pump provides an output voltage of ?5 v for currents loading in the range 0.5 ma i out 10 ma with a 15 v supply and 0.5 ma i out 7 ma with a 12 v supply. 06757-032 7 9 11 14 6 54 32 r1 510k? r3 470 ? d2 1n4001 r2 5.1k ? c1 0.02f c3 47f d1 1n4001 1n5231 5.1v zener c2 47f ?5v inverters = cd4049 10 12 15 + + figure 32. generating a C5 v supply when only 12 v or 15 v is available a single-supply, programmable current source the circuit in figure 33 shows how the AD5626 can be used with an op295 single-supply, rail-to-rail, output op amp to provide a digitally programmable current sink from v source that consumes less than 3.8 ma, maximum. the dac output voltage is applied across r1 by placing the 2n2222 transistor in the feedback loop of the op295. for the circuit values shown, the full-scale output current is 1 ma, which is given by the following equation: r1 d w i out v095.4 u where dw = the binary digital input code of the AD5626. 06757-033 cs clr sclk ldac sdin 2 8 6 5 3 4 1 7 AD5626 +5v v s 2n2222 load p1 200? r1 4.02k ? a1 = 1/2 op295 full-scale adjust 0.1f 5 v v dd a1 2 1 3 + ? v out gnd figure 33. a single-supply, programmable current source the usable output voltage range of the current sink is 5 v to 60 v. the low limit of the range is controlled by transistor saturation, and the high limit is controlled by the collector-base breakdown voltage of the 2n2222. galvanically-isolated interface in many process control type applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may occur. an i coupler? can provide isolation in excess of 2.5 kv. the serial loading structure of the AD5626 makes it ideal for isolated interfaces as the number of interface lines is kept to a minimum. figure 34 illustrates a 4-channel isolated interface using an adum1400 . for further information, visit http://www.analog.com/icouplers . encode decode encode decode encode decode v ia v ib v ic v id v oa v ob v oc v od encode decode a dum1 4 00* microcontroller serial clock out serial data out sync out control out to sclk to sdin to sync to ldac *additional pins omitted for clarity. 06757-034 figure 34. an i coupler-isolated dac interface
AD5626 rev. a | page 16 of 20 microprocessor interfacing AD5626 to mc68hc11 interface the circuit illustrated in figure 35 shows a serial interface between the AD5626 and the mc68hc11 8-bit microcontroller. sck of the mc68hc11 drives sclk of the AD5626, whereas the mosi output drives the serial data line, sdin, of the AD5626. the clr , ldac , and cs signals of the dac are derived from the pc1, pd5, and pc0 port lines, respectively, as shown. for correct operation of the serial interface, configure the mc68hc11 such that its cpol bit is set to 1 and its cpha bit is also set to 1. when the serial data is to be transmitted to the dac, pc0 is taken low, asserting the cs input of the dac. when the mc68hc11 is configured in this manner, serial data on mosi is valid on the rising edge of sclk. the mc68hc11 transmits its serial data in 8-bit bytes (msb first), with only eight rising clock edges occurring in the transmit cycle. to load data to the input serial register of the AD5626, pc0 is left low after the first eight bits are transferred, and a second byte of data is then transferred serially to the AD5626. during the second byte load, the first 4 msbs of the first byte are pushed out of the input shift register of the dac. at the end of the second byte load, pc0 is taken high. to prevent accidental advancing of the internal shift register, sclk must already be asserted before pc0 is taken high. to transfer the contents of the input shift register to the dac register, pd5 is taken low, asserting the ldac input. the clr input of the dac, controlled by the mc68hc11 pc1 port, provides an asynchronous clear function, setting the dac output to zero. 06757-035 * additional pins omitted for clarity. pc1 pc0 pd5 sck mosi mc68hc11* AD5626 clr cs ldac sclk sdin figure 35. AD5626 to mc68hc11 interface
AD5626 rev. a | page 17 of 20 outline dimensions compliant to jedec standards mo-187-aa 0.80 0.60 0.40 8 0 4 8 1 5 pin 1 0.65 bsc seating plane 0.38 0.22 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.08 3.20 3.00 2.80 5.15 4.90 4.65 0.15 0.00 0.95 0.85 0.75 figure 36. 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters 062507-a top view 8 1 5 4 0.30 0.23 0.18 exposed pad (bottom view) pin 1 index area 3.00 bsc sq seating plane 0.80 0.75 0.70 0.20 ref 0.05 max 0.02 nom 0.80 max 0.55 nom 1.74 1.64 1.49 2.48 2.38 2.23 0.50 0.40 0.30 0.65 bsc p i n 1 i n d i c a t o r ( r 0 . 1 9 ) figure 37. 8-lead lead frame chip scale package [lfcsp_wd] 3 mm x 3 mm body, very very thin, dual lead (cp-8-3) dimensions shown in millimeters ordering guide model inl (lsb) temperature range packag e description package option branding AD5626brmz 1 1 C40c to +85c 8-lead msop rm-8 dap AD5626brmz-reel7 1 1 C40c to +85c 8-lead msop rm-8 dap AD5626bcpz-reel7 1 1 C40c to +85c 8-lead lfcsp_wd cp-8-3 dap 1 z = rohs compliant part.
AD5626 rev. a | page 18 of 20 notes
AD5626 rev. a | page 19 of 20 notes
AD5626 rev. a | page 20 of 20 notes ?20072009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d06757-0-1/09(a)

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